1. Field of the Invention
This invention relates to a semiconductor memory device, and more particularly to a data output buffer used for a synchronous semiconductor memory device performing a data read/write operations in synchronism with an externally supplied clock.
2. Description of the Related Art
A dynamic RAM, a typical readable/writable memory, is essentially provided with a row address strobe (hereinafter referred to as "RAS") signal and a column address strobe (hereinafter referred to as "CAS") signal, respectively supplied from an external circuit such as a CPU, so as to read or write data from/into a memory cell therein.
FIG. 1A shows timing diagram for a read cycle in a conventional dynamic RAM. A row address signal RA is input to the memory device after a RAS signal has been enabled to "low" logic state followed by a column address signal CA being input in response to a CAS signal being enabled to "low" logic state while the RAS signal is held active. During this time, data stored in a memory cell corresponding to an address signal input is sensed by a sense amplifier. The data sensed is output through a data output buffer. When this takes place, data paths of the data output buffer are connected or disconnected according to an output enable signal OE (see FIG. 1B). It is well known that an output enable signal OE is generated by using a control clock supplied from a CPU and from a signal generated in the memory chip for data sensing.
In a conventional dynamic RAM, during one CAS cycle, only one bit of the output data is output in page mode while four bits of output data are output in nibble mode. Data output operations are inhibited once the RAS signal is disabled at which time the memory device enters a precharge mode. In practice, however, during every read cycle, a time interval (t.sub.RAC) spanning from an enabling point of the RAS signal to a point in time when the output data is substantially generated responding to the RAS signal, is essentially required. A data input/output line is equalized and precharged during the time interval from when data is output from the memory chip during an RAS cycle to when a next data is again output at the next RAS cycle. Thus, it should be apparent that the above mentioned time interval t.sub.RAC is much longer than a time required for equalizing and precharging the data input/output line. That is, a time loss is unnecessarily caused between a current data output cycle and a next data output cycle.
A conventional dynamic RAM also performs data access operations asynchronously. A data bus and an input/output bus are equalized and precharged at various time intervals between a current and a next read cycle, between a read and a write cycle, and between a current and a next write cycle. Moreover, a memory device formed on an integrated circuit receives TTL level signals provided from a CPU and converts them to CMOS level signals before using them. As is well known, present day CPU operation speeds are far more improved than the speeds of conventional memory devices. Manufacturers have as a result recognized the need to make the operation speeds of memory devices faster, which would result in shorter data access times.
However, the operation speed of a conventional asynchronous dynamic RAM can only be increased so much and no more given its unique operation structure. To solve the problem of slow data access times, a memory device is needed that is capable of carrying out a data read/write operation in synchronism with an external clock supplied from a CPU.